This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-297449, filed Sep. 28, 2000, the entire contents of which are incorporated herein by reference.
The present invention relates to a clock synchronous circuit suitable for devices such as clock synchronous type memories, e.g., a double-data-rate DRAM (DDR DRAM), synchronous DRAM (SDRAM), and double-data-rate, fast-cycle RAM, which perform synchronous control by using high-speed clocks.
Recent computer systems sometimes use a clock synchronous type memory such as a synchronous DRAM to meet demands for high-speed processing. Such a clock synchronous type memory internally uses a clock synchronized with a clock (external clock) which controls the memory.
If even a slight synchronous error is produced between the clock (internal clock) used inside the memory and the external clock especially during high-speed operation, internal circuits of the memory readily generate operation errors. Also, data output from the memory by using an internal clock having a synchronous difference interferes with high-speed processing of a controller which uses the data.
Accordingly, recent memories have a clock synchronous circuit for synchronizing an internal clock with an external clock with high accuracy inside a chip.
A memory having this clock synchronous circuit can stably perform high-speed operations. However, compared to a memory having no such clock synchronous circuit, the current consumption of the entire chip increases by an electric current consumed by the clock synchronous circuit. To alleviate this handicap, when the internal clock generated by the clock synchronous circuit is not used by internal circuits of the memory, it is necessary to stop the operation of the clock synchronous circuit as much as possible and thereby reduce the current consumption of the entire chip.
A clock synchronous circuit of an aspect of the present invention comprises a receiver for receiving an external clock, a delay monitor which receives an output signal from the receiver and has a delay time equal to the sum of the delay time of the receiver and the delay time of a circuit as an object of delay control, a first delay line which comprises a plurality of series-connected first delay units and delays an output signal from the delay monitor by a predetermined time, a second delay line which comprises a plurality of series-connected second delay units, and outputs a signal obtained by delaying the output signal from the delay monitor by the predetermined time and again delaying the output signal from the delay monitor by the predetermined time, and outputs the signal, an input interrupting circuit for determining start and stop of the first and second delay lines, and a control circuit for controlling the operation of the input interrupting circuit.